FIG. 1 shows an integrated semiconductor memory device 1000 which is in the form of a DRAM (dynamic random access memory) semiconductor memory, for example. The integrated semiconductor memory device comprises a memory cell array 100 in which memory cells are arranged in matrix form along word lines and bit lines. FIG. 1 shows two memory cells SZ1 and SZ2 by way of example, these being connected between a word line WL and a bit line BL1 or BL2. A DRAM memory cell comprises a selection transistor AT and a storage capacitor SC. An appropriate control signal on the word line WL can be used to turn on the selection transistor AT, so that the storage capacitor SC is conductively connected to the bit line which is connected to it.
To control read and write access operations to the memory cells in the integrated semiconductor memory device, a control circuit 200 is used which is connected to an external connection A for applying a control signal /CS, to an external connection B for applying a control signal /RAS, to an external connection C for applying an external control signal /CAS and to an external connection D for applying a control signal /WE. In addition, the control circuit 200 is connected to a clock connection T1 for applying a clock signal CLK and to a clock connection T2 for applying a clock signal bCLK. To select a memory cell within the memory cell array 100, the integrated semiconductor memory device has an address register 300 with an external connection E for applying an address signal AD.
FIG. 2 shows the waveform of the control signals /CS, /RAS, /CAS and /WE for reading data in and out at a data connection DQ of the integrated semiconductor memory device. In this case, the control signals are applied in sync with the waveform of a control clock which is formed from the clock signals CLK and bCLK.
To perform a write access operation to one of the memory cells SZ, which is able to be selected by applying the address AD at the external connection E of the address register 300, an activation signal ACT is applied to the integrated semiconductor memory device during a first clock period 1. The activation signal ACT is formed from a signal combination of the control signals /CS and /RAS. Following evaluation of the activation signal ACT, the selection transistors AT in the memory cells which are arranged along the word line selected using the address AD are turned on. To select a memory cell along the word line WL, the signal combination WRITE, which is formed from the control signals /CS, /CAS and /WE, is applied to the external connections of the integrated semiconductor memory device within a clock period 2. When the appropriate address AD is used to select the memory cell SZ1, for example, the bit line BL1 is connected to the data connection DQ via a sense amplifier (not shown in FIG. 1). Within a clock period 3, a data item which is present at the data connection DQ is read into the memory cell SZ1.
The clock periods 6, 7 and 8 show the waveform of the external control signals during read access to one of the memory cells. To assess a potential level on the bit lines, these are charged to a common precharge potential within the clock period 6 by the signal combination PRE, which is formed from the control signals /CS, /RAS and /WE. During the clock period 7, in similar fashion to write access, the activation signal ACT, which is formed from the control signal /CS and /RAS, is again applied to the external connections of the integrated semiconductor memory device. As a result of the activation signal ACT, a word line is activated along which the selection transistors in the memory cells are turned on. To select one of the memory cells which are arranged along the word line WL, the signal combination READ, which is formed from the control signal /CS and /CAS, is applied to the integrated semiconductor memory device within a clock period 8 for read access. In line with the applied address, the control circuit 200 then selects a memory cell along the selected word line for read access.
As FIG. 2 shows, the control signal combinations ACT, WRITE, PRE and READ are always applied within one clock period of the control clock. The control clock is formed from a clock signal CLK and a clock signal bCLK, whose waveform is complementary to that of the clock signal CLK. At every second crossover point for the clock signals with complementary waveforms, a new clock period starts. To operate the integrated semiconductor memory device in sync with the waveform of the control clock, the two clock signals CLK and bCLK need to assume a high and a low level in complementary fashion with respect to one another. If one of the clock signals does not assume the full high or low level or even an approximately static value, this may result in a shift in the crossover points for the two clock signals. Level fluctuations in the clock signals CLK and bCLK have a particularly problematic effect. Such level fluctuations lengthen or shorten the times for applying the command signals ACT, WRITE, PRE and READ. There is thus the disturbance in the errorfree reading of data into and out of a memory cell array in an integrated semiconductor memory device.